Analysis and Minimization of Substrate Spurs in Fractional-N Frequency Synthesizers

This paper analyses substrate-related spurious tones in fractional-N phaselocked loops with integrated VCOs. Spur positions are calculated and experimentally verified as a function of the divider ratios of prescaler and programmable divider. For an integrated wideband PLL in SiGe BiCMOS technology the spur power levels are measured and compared with theoretical expectations. The power in these spurs is minimized by layout techniques shielding the reference input buffer. Spur minimization by using a variable reference frequency is experimentally demonstrated. Based on this observation, a programmable integer-N PLL for driving the fractional-N synthesizer is suggested to reduce the worst-case spur level significantly. Index Terms — Fractional-N, frequency synthesizers, fractional spurs, substrate spurs, phase-locked loops (PLLs), phase noise.